ABOUT OLIX AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance. THE ROLE We are designing silicon for a new and innovative breakthrough AI computing solution using optics and high-speed interconnect. Verifying the mixed-signal subsystems of this solution is one of the hardest and highest-leverage problems in the design flow and it is where this role sits. As a Senior Mixed-Signal Verification Engineer, you will own the verification of analog and mixed-signal blocks across our high-speed IO RX/TX chains - CDRs, phase interpolators and clock generation, DFE/CTLE equalization, samplers and slicers, deserializers, and the digital control loops that wrap around them. You will work at the boundary where analog behavior meets digital control, building the models, environments, and methodology that let us find bugs in silicon-accurate simulation rather than in the lab. RESPONSIBILITIES * Own the verification strategy and test plan for our mixed-signal subsystems, from block level through subsystem and top-level integration. * Define the modeling approach and fidelity tiers - decide what gets a real-number model, what needs Verilog-AMS, and where transistor-level co-sim is required - and document the accuracy/runtime trade-offs. * Develop and validate analog behavioral models against transistor-level references, owning the model-vs-schematic equivalence checks that keep the abstraction honest. * Build self-checking testbenches and reusable verification components for analog/digital interactions: CDR lock, adaptation and calibration loop convergence, mode and power-state transitions, clock dividers, deserializers, and clock-domain crossings. * Drive AMS co-simulation flows (Spice/FastSpice coupled with digital simulators) and own their setup, performance, and runtime trade-offs. * Define functional coverage and assertions that target analog corner behavior - saturation, overflow, polarity, loop stability, settling - not just digital state. * Debug and root-cause failures across the analog/digital boundary, including discrepancies between behavioral and transistor-level results, and drive them to closure. * Partner with analog and DSP designers to review specs, pin down interface contracts, and translate analog intent into checkable models, assertions, and tests. * Own block- and subsystem-level verification sign-off for tape-out, including coverage closure and a clear statement of what AMS did and did not verify (functional vs. performance). * Build and maintain regression infrastructure and flow automation, and improve AMS simulation throughput. * Contribute to silicon bring-up and lab correlation, feeding measured behavior back into model validation. SKILLS & EXPERIENCE * BS/MS in Electrical Engineering or related field, with 5+ years of analog/mixed-signal verification experience on complex SoCs or mixed-signal IP. * Hands-on expertise with AMS modeling and verification: Verilog-AMS and real-number modeling (SystemVerilog real / wreal), and analog-digital co-simulation flows (e.g., Spectre AMS, FastSpice coupled with a digital simulator). * Proficiency in SystemVerilog, with solid assertion-based verification skills and the ability to architect self-checking testbenches and reusable verification components. * Demonstrated ability to model analog blocks at the appropriate level of abstraction and to validate those models against transistor-level references. * Strong debug skills across the analog/digital boundary, with a structured approach to test planning, functional coverage, and closure. * Comfort reading analog schematics and specifications and collaborating directly with analog and DSP designers. NICE TO HAVE * Strong working knowledge of high-speed SerDes / wireline architectures - CDR and clock recovery, equalization (CTLE, DFE), PLLs and clocking, samplers/slicers, and serialization/deserialization. * Experience verifying calibration and adaptation loops (offset and I/Q calibration, DFE tap adaptation) and clock-domain-crossing logic between recovered and core clock domains. * UVM or other constrained-random, metric-driven verification experience for the digital control wrapped around analog blocks. * Scripting for regression and flow automation (Python, TCL, Make). * Track record of mixed-signal IP sign-off through tape-out, plus silicon bring-up and measurement correlation. * A clear understanding of where AMS verification ends and transistor-level performance sign-off begins. COMPENSATION & EQUITY * Competitive Salary: Commensurate with your experience, skills, and location * Equity & Ownership: Meaningful stock options. You’re not just joining the mission; you’re owning a piece of it * Proximity Bonus: We value your time. To minimise your commute and maximise your life, we offer an annual Living-Local Bonus if your residence is within 20 minutes of the office * Retirement Benefits: Employer-contributed retirement plans to help you build long-term financial security Due to U.S. export control regulations, candidates’ eligibility to work at OLIX depends on their most recent citizenship or permanent residency status. We are generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, and Venezuela). Applicants who have subsequently obtained citizenship or permanent residency in another country not subject to these restrictions may still be eligible.