We're hiring an HPC SoC Timing Design Engineer/Leader for a global semiconductor company developing flagship automotive SoCs — large-scale chips integrating CPU, cache, memory, high-speed interfaces, AI, video, functional safety, and security — powering the intelligence and electrification of next-generation vehicles. About the role High-performance SoC products, also used in automobiles, are key components for realizing the electronic and high-performance capabilities of vehicles, exemplified by "CASE" (Connected, Autonomous, Shared, and Electric). With the increasing demand for improved functionality and performance, SoCs are becoming larger and more complex. Competition is intensifying with the entry of semiconductor vendors from non-automotive sectors, making cost competitiveness a challenge. From a timing design perspective, efficient development of large-scale, complex SoC products with short turnaround times is essential, and we are seeking engineers/leaders who can develop products innovatively. Furthermore, since design is carried out in collaboration with design centers in Vietnam and India (language: English), we are looking for engineers who can thrive globally. RESPONSIBILITIES Design Engineer or Design Leader for SoC Timing Design (STA, SDC, Synthesis). Timing design (static timing analysis, timing constraint analysis, logic synthesis technology development, product application). Static timing analysis: Timing design using commercially available STA tools. Timing constraint analysis: Validation of timing constraints using commercially available STA tools and in-house developed tools. Logic synthesis: Logic synthesis using commercially available logic synthesis tools. ★In all cases of static timing analysis, timing constraint analysis, and logic synthesis, they collaborate with overseas offices. JOB SATISFACTION In Physical Design roles, managers are deeply involved in the actual design process, driving product development and improving the development flow. Working closely with the design team, you will play a crucial role in finalizing LSI product designs. They utilize the cutting-edge 3nm process node for automotive applications, and they pride themselves on offering top-level challenges and rewards in digital backend design. Furthermore, their collaboration with overseas EDA vendors and design centers allows you to participate in their work as part of a global organization. DESIRED CANDIDATE PROFILE Those who have the attitude to face difficulties head-on. People with strong leadership skills. Someone who can see the big picture. Those with strong solution proposal skills. Those who are comfortable using English in their work. QUALIFICATIONS 【MUST】 Over 5 years of experience in digital LSI design (including over 3 years of experience in timing design (static timing analysis, timing constraint analysis)). Either English or Japanese at a business level (the other at a conversational level). 【WANT】 Understanding hardware description languages (e.g., Verilog-HDL) Experience using English in a professional setting Management experience Those interested in management in the future ADDITIONAL INFORMATION *Details regarding the scope of changes to the work location and the scope of duties to be performed will be provided during the selection process. Location: Kodaira, Japan