IC/RTL Design Engineer

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San Jose Full-time Posted 30+ days ago

IC/RTL Design Engineer/ Front-End Engineer What you'll do * Develop block-level micro-architecture for your assigned blocks, and contribute to interface and register definitions. * Design and implement front-end RTL blocks in SystemVerilog — datapath elements, the UCIe streaming/RDI adapter, elastic FIFOs, and supporting logic. * Integrate IP and support parameterization for configurability. * Write clean, lint-clean, CDC/RDC-clean RTL that follows the coding and quality standards. * Write block-level testbenches, sanity checks, and assertions (SVA) for your own blocks before handoff to…

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