MEET ARAGO AND THE ARAGONIANS Arago is an AI and computer hardware company whose mission is to drive the course of history forward. We do so by accelerating breakthroughs at the intersection of AI and semiconductors. Founded in 2024 by AI researchers and physicists with deep expertise in photonics, electronics, software, mathematics, and machine learning, Arago brings together a lean team of engineers and scientists from the world’s top companies and research labs. Composed of nine nationalities and operating from hubs in France, North America, and Israel, we believe in great science and fast achievements. Our work is guided by these core principles: 1. Do great things: we deliver work we’re proud to sign our name to. 2. High velocity: speed matters. We move quickly, one step at a time. 3. One unit: we’re all in this together, with relationships grounded in trust, respect, and camaraderie. Arago is backed by executives from Apple, Arm, Nvidia, Microsoft, and Hugging Face, as well as prominent US and European deeptech venture firms and exited founders. WHAT YOU’LL DO Work on the definition and realization of next-generation compute architectures by driving system-level design, guiding cross-functional engineering teams, and delivering silicon from first concept to production. RESPONSIBILITIES * Carry the top-level architecture of Arago’s multiphysics compute platform, including processing elements, interconnects, memory subsystems, and system-level control. * Own the architectural vision from concept through tape-out, driving system modeling, specification, and implementation handoff across engineering teams. * Work and mentor cross-functional hardware teams across RTL design, functional verification, and physical integration to ensure consistent technical direction and execution quality. * Collaborate with software, packaging, and system integration teams to ensure architectural choices support overall platform scalability, performance, and reliability. * Evaluate new architectural directions, develop performance and cost models, and guide prototyping efforts to de-risk innovations for future product generations. REQUIRED SKILLS AND EXPERIENCE * Proven track record in architecting complex, high-performance digital systems such as multicore processors, vector engines, and domain-specific accelerators. * Deep expertise in computer architecture, including memory hierarchies, interconnects, cache coherence, instruction set design, and performance-power-area trade-offs. * Hands-on experience with the design and integration of compute-intensive blocks such as vector arithmetic logic units (ALUs), SIMD pipelines, systolic arrays, and custom datapaths for signal or tensor processing. * Experience in leading full ASIC development cycles from architectural concept and modeling through RTL implementation, functional verification, physical design, and tape-out. * Experience with advanced system integration and packaging technologies such as HBM, chiplets, and 2.5D/3D integration, with a strong understanding of their architectural and system-level impact, is highly valued. * Strong leadership and communication skills, with the ability to align multidisciplinary teams (architecture, RTL, verification, software, and physical design) under a unified vision. PAY AND BENEFITS * Competitive cash compensation, with final package based on location, experience, and the pay of team members in similar positions. * Meaningful stock option plan offered at the earliest stage of the company (included in the majority of full time offers). * Relocation bonus and coverage of moving expenses for relocation within 20 minutes of the company’s location. * Healthcare coverage (including family-friendly options), pension contributions, professional development support, and 25 days of PTO, in addition to public holidays. * Ownership of a key technical domain, with significant vertical and/or horizontal growth opportunities, based on performance and individual drive. * A high-paced, multicultural (with 9 nationalities), and engineering-led environment.

Senior ASIC Architect

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