Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Tech Lead Design Verification Engineer – CXL / PCIe / Ethernet About Astera Labs Astera Labs is a global leader in semiconductor-based connectivity solutions purpose-built for AI and cloud infrastructure. Our intelligent connectivity platform enables hyperscalers and system OEMs to unlock the full potential of accelerated computing through industry-leading technologies such as Compute Express Link (CXL), PCI Express (PCIe), and Ethernet. We are looking for a highly motivated Tech Lead Design Verification Engineer to join our Silicon Engineering team and drive the verification of next-generation connectivity IPs and SoCs that power AI infrastructure and cloud-scale systems. Role Overview As a Lead Design Verification Engineer, you will lead the verification of complex digital IPs and SoC subsystems, ensuring high-quality, first-pass silicon. You will own verification planning, environment development, test execution, debugging, and sign-off while working closely with Architecture, Design, Firmware, Emulation, and Validation teams. This role requires strong technical expertise, hands-on verification experience, and the ability to mentor engineers and drive execution across multiple projects. Key Responsibilities Verification Leadership * Lead the verification of complex IPs and SoC subsystems from specification through tape-out. * Develop comprehensive verification plans based on architectural and functional specifications. * Own verification execution, coverage closure, regression management, and verification sign-off. * Drive verification milestones while ensuring quality and schedule commitments. Verification Development * Design and develop scalable UVM/SystemVerilog verification environments. * Develop reusable verification components including agents, drivers, monitors, scoreboards, assertions, and coverage models. * Create constrained-random and directed test scenarios to verify functionality and corner cases. * Drive functional and code coverage closure. Protocol Verification Verify one or more of the following protocols: * Compute Express Link (CXL) * PCI Express (Gen4/Gen5/Gen6) * Ethernet (10G/25G/50G/100G/200G/400G) * AXI, APB, AHB * High-speed SerDes interfaces * DDR/LPDDR/HBM interfaces (preferred) Debug & Quality * Debug RTL, protocol, and integration issues using simulation and waveform analysis. * Develop SystemVerilog Assertions (SVA) and protocol checkers. * Analyze regression failures and drive root-cause resolution with Design teams. * Ensure verification completeness and high-quality tape-out readiness. Cross-Functional Collaboration * Work closely with Architecture teams to review specifications and verification requirements. * Partner with RTL designers during implementation and debug. * Collaborate with Firmware, Validation, Emulation, and Post-Silicon teams to support product bring-up. * Participate in architecture, design, and verification reviews. Required Qualifications * Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field. * 6–12+ years of experience in Design Verification. * Strong expertise in SystemVerilog and UVM. * Experience developing constrained-random, coverage-driven verification environments. * Strong understanding of digital design fundamentals and computer architecture. * Hands-on experience with assertions (SVA), functional coverage, and verification sign-off. * Strong debugging skills using simulation tools and waveform analysis. * Experience with Synopsys VCS, Cadence Xcelium, or Siemens Questa simulators. Preferred Technical Skills * Experience verifying CXL, PCIe, Ethernet, or other high-speed connectivity protocols. * Knowledge of SoC verification methodologies and subsystem integration. * Familiarity with cache coherency and high-speed interconnects. * Experience with Formal Verification, CDC/RDC verification, and low-power verification. * Knowledge of scripting languages such as Python, Perl, Tcl, or Shell. * Experience with CI/CD pipelines and regression automation. * Exposure to emulation or FPGA-based verification is a plus. Preferred Experience * Verification experience on networking, connectivity, storage, or AI accelerator SoCs. * Experience delivering multiple successful silicon tape-outs. * Working knowledge of AI infrastructure or data center technologies. * Ability to independently lead verification efforts for complex IPs or SoC subsystems. Why Astera Labs? At Astera Labs, you'll help build the connectivity solutions that power the world's most advanced AI and cloud platforms. You'll work on cutting-edge technologies, collaborate with exceptional engineers, and have the opportunity to influence products that are shaping the future of accelerated computing. If you're passionate about solving complex verification challenges and delivering world-class silicon, we'd love to hear from you.   We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.